PhD (Electrical Engineering)Sherbrooke University, Canada
Master’s in Electrical EngineeringConcordia University, Montreal, Canada
Bachelor of Engineering in Electronics and CommunicationL.D. College of Engineering, Gujarat University, India.
Assistant ProfessorDhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, India.
ASIC EngineereInfochips, Ahmedabad, India
Research AssistantDepartment of Engineering Physics & Department of Material Science, Ecole Polytechnic, Montréal, Canada
Technical Support RepresentativeVolt at HP, Kirkland, Quebec, Canada
LecturerComputer / IT Department, Nirma University, Ahmedabad, India
Centre ManagerGujarat Infotech Limited, Ahmedabad, India.
Develop models, codesign methodology and cosimulation of hybrid circuits of emerging nanoelectronic devices with CMOS technology, low voltage low power circuits, Phase Change Memory, MEMS devices and embedded systems.
- Thakkar, P. Rajput, R. Dubey and R. Parekh, “Design and Implementation of Autonomous UAV Tracking System Using GPS and GPRS”, 2nd International Conference on Advanced Computing and Intelligent Engineering, India, 23-25 November, 2017. Best Springer paper award in Intelligent Networking Track.
- Parekh, M. S. Baghini and B. Rajendran, “Modeling and simulation of 1/f noise during threshold switching for Phase Change Memory”, Lecture Notes in Electrical Engineering (LNEE), First International Conference on Advanced Computational and Communication Paradigms (ICACCP),India, 08-10 September 2017.
- Gargave, Y. Agrawal, R. Parekh, “Single Precision Floating Point Matrix Multiplier using Low Power Arithmetic Circuits”, Lecture Notes in Electrical Engineering (LNEE), 1st Springer International Conference on Emerging Trends and Advances in Electrical Engineering and Renewable Energy (ETAEERE-2016), India, 17 – 18 Dec, 2016. DOI: 10.1007/978-981-10-4394-9_67
- Parekh, A. Beaumont, J. Beauvais, and D. Drouin, “Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room Temperature Operation”, IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp. 918-923, 2012.DOI: 10.1109/TED.2012.2183374, Citations : 16
- Parekh,J. Beauvais, and D. Drouin, “SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit”, Microelectronics Journal, 45, pp. 1087-1092, 2014. DOI: 10.1016/j.mejo.2014.05.020, Citations : 5.
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